1 of 10 071700 features halts and restarts an out-of-control microprocessor holds microprocessor in check during power transients automatically restarts microprocessor after power failure monitors pushbutton for external override accurate 5%, 10% or 20% resets for 3.3v systems and 5% or 10% resets for 5.0v systems eliminates the need for discrete components 3.3v 20% tolerance for use with 3.0v systems pin-compatible with the maxim max705/max706 in 8-pin dip, 8-pin soic, and -sop 8-pin dip, 8-pin soic and 8-pin -sop packages industrial temperature range -40 c to +85 c pin assignment DS1705 and ds1706_r/s/t (*ds1706l and ds1706p) pin description pbrst - pushbutton reset input v cc - power supply gnd - ground in - input nmi - non-maskable interrupt st - strobe input rst - active low reset output *rst - active high reset output (ds1706p and ds1706l only) wds - watchdog status output description the DS1705/ds1706 3.3- or 5.0-volt micromonitor monitors three vital conditions for a microprocessor: power supply, software execution, and external override. a precision temperature compensated reference and comparator circuit monitor the status of v cc at the device and at an upstream point for maximum protection. when the sense input detects an out-of-tolerance condition a non-maskable interrupt is generated. as the voltage at the device degrades, an internal power fail signal is generated which forces DS1705/ds1706 3.3 and 5.0 volt micromonito r www.dalsemi.com 8-pin rst(*rst) wds pbrst v cc st nmi in gnd 1 2 3 4 8 7 6 5 8-pin dip (300 -mil) pbrst v cc gnd in wds rst st nmi 1 2 3 4 8 7 6 5 8-pin soic (150-mil) 1 2 3 4 8 7 6 5 pbrst v cc gnd in wds rst(*rst) st nmi
DS1705/ds1706 2 of 10 the reset to an active state. when v cc returns to an in-tolerance condition, the reset signal is kept in the active state for a minimum of 130 ms to allow the power supply and processor to stabilize. the second function the DS1705/ds1706 performs is pushbutton reset control. the DS1705/ds1706 debounces the pushbutton input and guarantees an active reset pulse width of 130 ms minimum. the third function is a watchdog timer. the DS1705/ds1706 has an internal timer that forces the wdo signal to the active state if the strobe input is not driven low prior to time-out. operation power monitor the DS1705/ds1706 detects out-of-tolerance power supply conditions and warns a processor-based system of impending power failure. when v cc falls below the minimum v cc tolerance, a comparator outputs the rst (or rst) signal. rst (or rst) is an excellent control signal for a microprocessor, as processing is stopped at the last possible moment of valid v cc . on power-up, rst (or rst) are kept active for a minimum of 130 ms to allow the power supply and processor to stabilize. pushbutton reset the DS1705/ds1706 provides an input pin for direct connection to a pushbutton reset (see figure 2). the pushbutton reset input requires an active low signal. internally, this input is debounced and timed such that a rst (or rst) signal of at least 130 ms minimum will be generated. the 130 ms delay commences as the pushbutton reset input is released from the low level. the pushbutton can be initiated by connecting the wds or nmi outputs to the pbrst input as shown in figure 3. non-maskable interrupt the DS1705/ds1706 generates a non-maskable interrupt ( nmi ) for early warning of a power failure. a precision comparator monitors the voltage level at the in pin relative to an on-chip reference generated by an internal band gap. the in pin is a high impedance input allowing for a user-defined sense point. an external resistor voltage divider network (figure 5) is used to interface with high voltage signals. this sense point may be derived from a regulated supply or from a higher dc voltage level closer to the main system power input. since the in trip point v tp is 1.25 volts, the proper values for r1 and r2 can be determined by the equation as shown in figure 5. proper operation of the DS1705/ds1706 requires that the voltage at the in pin be limited to v cc . therefore, the maximum allowable voltage at the supply being monitored (v max ) can also be derived as shown in figure 5. a simple approach to solving the equation is to select a value for r2 high enough to keep power consumption low, and solve for r1. the flexibility of the in input pin allows for detection of power loss at the earliest point in a power supply system, maximizing the amount of time for system shutdown between nmi and rst (or rst). when the supply being monitored decays to the voltage sense point, the DS1705/ds1706 pulses the nmi output to the active state for a minimum 200 s. the nmi power-fail detection circuitry also has built-in hysteresis of 100 v. the supply must be below the voltage sense point for approximately 5 s before a low nmi will be generated. in this way, power supply noise is removed from the monitoring function, preventing false interrupts. during a power-up, any detected in pin levels below v tp by the comparator are disabled from generating an interrupt until v cc rises to v cctp . as a result, any potential nmi pulse will not be initiated until v cc reaches v cctp . connecting nmi to pbrst would allow non-maskable interrupt to generate an automatic reset when an out-of-tolerance condition occurred in a monitored supply. an example is shown in figure 3.
DS1705/ds1706 3 of 10 watchdog timer the watchdog timer function forces wds signals active when the st input is not clocked within the 1 second time-out period. time-out of the watchdog starts when rst (or rst) becomes inactive. if a high- to-low transition occurs on the st input pin prior to time-out, the watchdog timer is reset and begins to time out again. if the watchdog timer is allowed to time out, the wds signal is driven active (low) for a minimum of 130 ms. the st input can be derived from many microprocessor outputs. the typical signals used are the microprocessors address signals, data signals, or control signals. when the microprocessor functions normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to time-out. to guarantee that the watchdog timer does not time out, a high-to-low transition must occur at or less than the minimum watchdog time-out of 1 second. a typical circuit example is shown in figure 6. micromonitor block diagram figure 1 push-button reset figure 2
DS1705/ds1706 4 of 10 push-button reset controlled by nmi and wds figure 3 timing diagram: pushbutton reset figure 4 non-maskable interrupt circuit example figure 5 v sense = r2 r2 r1 + x 1.25 v max = tp sense v v x v cc example: v sense = 4.50v at the trip point v cc = 3.3v 10 k = r2 therefore: 25 . 1 50 . 4 x 3.3 = 12.4v maximum 4.5 = 10 k 10k r1 + x 1.25 r1 = 26 k
DS1705/ds1706 5 of 10 watchdog timer figure 6 timing diagram: strobe input figure 7 timing diagram: non-maskable interrupt figure 8
DS1705/ds1706 6 of 10 timing diagram: power-down figure 9
DS1705/ds1706 7 of 10 timing diagram: power-up figure 10
DS1705/ds1706 8 of 10 absolute maximum ratings* voltage on v cc pin relative to ground -0.5v to +7.0v voltage on i/o relative to ground** -0.5v to v cc + 0.5v operating temperature -40 c to +85 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ** the voltage input on in, st, and pbrst can be exceeded if the input current is less than 10 ma. recommended dc operating conditions (-40 c to +85 c) parameter symbol min typ max units notes supply voltage v cc 1.2 5.5 v 1 st and pbrst input high level v ih 2.0 v cc -0.5 v cc +0.3 v 1, 3 1, 4 st and pbrst input low level v il -0.03 +0.5 v 1 dc electrical characteristics (-40 c to +85 c; v cc =1.2v to 5.5v) parameter symbol min typ max units notes v cc trip point DS1705/ds1706l v cctp 4.50 4.65 4.75 v 1 v cc trip point ds1706 v cctp 4.25 4.40 4.50 v 1 v cc trip point ds1706t v cctp 3.00 3.08 3.15 v 1 v cc trip point ds1706s v cctp 2.85 2.93 3.00 v 1 v cc trip point ds1706p or r v cctp 2.55 2.63 2.70 v 1 input leakage i il -1.0 +1.0 a 2 output current @ 2.4v i oh 350 a 3 output current @ 0.4v i ol 10 ma 3 output voltage @ -500 a v oh v cc +-0.3 v cc -0.1 v 3 operating current @ v cc < 5.5v i cc 60 a 5 operating current @ v cc < 3.6v i cc 50 a 5 in input trip point v tp 1.20 1.25 1.30 v 1 capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 5pf output capacitance c out 7pf
DS1705/ds1706 9 of 10 ac electrical characteristics (-40 c to +85 c; v cc =1.2v to 5.5v) parameter symbol min typ max units notes pbrst = v il t pb 150 ns reset active time t rst 130 205 285 ms st pulse width t st 10 ns 6 v cc detect to rst and rst t rpd 58 s 9 v cc slew rate t f 20 s v cc detect to rst and rst t rpu 130 205 285 ms 7 v cc slew rate t r 0ns pbrst stable low to rst and rst t pdly 250 ns watchdog timeout t td 1.0 1.6 2.2 s 8 vin detect to nmi t ipd 58 s 9 notes: 1. all voltages are referenced to ground. 2. pbrst is internally pulled up to v cc with an internal impedance of 40 k ? = typical and the st input is internally pulled up to v cc with an internal impedance of 180 k ? = typical. 3. v cc 2.4v. 4. v cc < 2.4v. 5. measured with outputs open and all inputs at v cc or ground. 6. must not exceed t td minimum. 7. t r = 5 s. 8. minimum watchdog time-out tested at 2.7v for the 3.3v devices and 4.5v for the 5.0v devices. 9. noise immunity ? pulses < 2 s at v cctp minimum will not cause a reset.
DS1705/ds1706 10 of 10 part marking codes 8-pin -sop (118 mil) a, b, c and d represents the device type and tolerance. abcd 705_ - DS1705 706_ - ds1706 706l - ds1706l 706p - ds1706p 706r - ds1706r 706s - ds1706s 706t - ds1706t wwy represents the device manufacturing work w eek, y ear.
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